Honda Motor and Renesas Electronics recently announced signing an agreement which will see both companies develop a high-performance system-on-chip (SoC) for software-defined vehicles (SDVs).
The new SoC is designed to deliver AI performance of 2,000*2 TOPS combined with a world-class power efficiency of 20 TOPS/W, and is slated for use in future models of the “Honda 0 (Zero) Series,” Honda’s new electric vehicle (EV) series, specifically those that will be launched in the late 2020s. The agreement was announced during a Honda press conference that took place at CES 2025 in Las Vegas, Nevada on 7th January.
To realise the Honda vision for SDVs, Honda and Renesas reached an agreement to develop a high-performance SoC compute solution designed for core ECUs. Using TSMC’s 3-nm automotive process technology, this SoC also can achieve a significant reduction in power consumption.
Furthermore, it realises a system that utilises multi-die chiplet technology to combine Renesas’ generic fifth-generation (Gen 5) R-Car X5 SoC series with an AI accelerator optimised for AI software developed independently by Honda. Using this combination, the system aims to achieve one of the industry’s top class AI performances with power efficiency. The SoC chiplet solution will provide the AI performance required for advanced functions such as AD, while keeping power consumption low. Chiplet technology allows the flexibility to create customised solutions and offers future upgrades for functional and performance improvements.
This marks a strenghtening of the relationship between Honda and Renesas, that have collaborated closely for many years. The agreement will accelerate the integration of advanced semiconductor and software innovations into the Honda 0 Series.
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