AI’s explosive compute demands are reshaping data centre networks, pushing the industry beyond fragmented protocols towards unified fabrics, where physical interconnect innovation defines scalable performance, writes Vivek Shah, Senior Director of Advanced Technologies at Molex.
The intense processing requirements of AI are ushering in a new era for traditional data centre networks, moving the industry beyond today’s complex patchwork of protocols,
A segment of the industry is now drafting the blueprint for a new architecture called the unified fabric. Bringing this powerful concept to life, however, demands a total transformation of the physical interconnects that comprise its structure.
Performance gains in AI processors have shifted the network bottleneck from compute to connectivity. The data centre’s network fabric—the high-speed communication infrastructure of switches, optics and cabling that connects processors, accelerators and memory—has now emerged as the critical constraint on scaling AI networks.
Today’s high-performance data centres rely on a patchwork of specialised interconnect technologies such as PCIe, NVLink, Ethernet and the emerging Compute Express Link (CXL). Each excels within its domain, but stitching these protocols together introduces latency, power inefficiencies and management complexity that limit overall system performance.
The industry’s answer is a unified fabric architecture: a vision of converged connectivity that treats the entire data centre as a single, coherent compute system. This shifts the critical engineering challenge from software orchestration to the physical layer. Connectors, optics and cabling must now handle massive data volumes, signal integrity and thermal demands that come with AI-scale computing.
Why today’s patchwork falls short
Today’s AI data centre connectivity strategy is a collection of specialized protocols where the whole delivers less efficiency than the sum of its parts. Each protocol—from PCIe and NVLink to Ethernet and CLX—is optimized for its own domain, but data must traverse multiple layers to move between compute, memory and storage resources. Every transition introduces latency, buffering and translation overhead that collectively throttle AI training performance and leave valuable compute resources underutilised.
The specific limitations of each interconnect highlight the challenges of heterogeneous AI fabrics. NVLink delivers exceptional GPU-to-GPU bandwidth within a server but does not natively scale across nodes. Ethernet and InfiniBand provide the required rack-to-rack and cluster connectivity, yet their protocol stacks and CPU-driven data handling introduce significant software overhead and latency penalties compared to native GPU fabrics. PCIe and the emerging CXL standard offer versatility for peripherals and memory, but they function primarily as specialized extensions for specific tasks rather than high-bandwidth GPU communication.
A new vision for AI data center connectivity: the unified fabric
The industry’s vision for solving the patchwork problem is the unified fabric: a design that converges multiple specialized protocols into a single, high-performance network for AI-critical data traffic. The guiding principle is radical simplification. Rather than maintaining separate domains for PCIe, NVLink and Ethernet, a unified fabric creates a flat, composable network that seamlessly carries compute, storage and memory traffic across the data centre.
This architecture materializes the “SuperNode” concept, which treats the entire cluster as a dynamically reconfigurable resource pool. In this model, a GPU in one rack can directly access memory in another with minimal overhead; storage traffic is consolidated into the same high-performance fabric, and compute resources can be dynamically reconfigured to maximize utilisation.
Multiple major industry initiatives are advancing this vision. These range from specific vendor proposals like Huawei’s UB-Mesh, which aims for more than 10Tbps of bandwidth per ASIC with sub-microsecond latency, to broader collaborative efforts like the Ultra Ethernet Consortium.
The tangible outcomes directly address the inefficiencies of the current patchwork approach: significantly lower latency accelerates large-scale AI training, simplified infrastructure reduces operational overhead and dynamic resource allocation minimizes idle or underutilized hardware.
The physical layer challenge of AI data centre connectivity
While the unified fabric represents a powerful architectural concept, its realization shifts the primary engineering challenges to the physical layer, introducing a new class of demands across the entire interconnect path. At the on-chip I/O level, the massive bandwidth requirements are driving the adoption of co-packaged optics (CPO), where optical transceivers are integrated directly adjacent to the processor.
This approach, while improving data throughput and energy efficiency, introduces new challenges in thermal management, power delivery and serviceability.
Within the internal signal path, routing 224 Gbps PAM-4 signals across conventional PCBs can quickly become a performance bottleneck, as higher data rates exacerbate signal degradation and impair overall system reliability. At the rack level, scaling fabrics across thousands of nodes requires advanced pluggable connectors and ultra-dense cabling capable of supporting 1.6 Tb per port while preserving signal integrity.
Beyond the hardware, next-generation fabrics must also overcome broader ecosystem challenges ensuring interoperability with existing standards, enabling widespread adoption and maintaining vendor neutrality across diverse deployment environments.
Building the foundation for AI data centre connectivity
Meeting the physical demands of a unified fabric requires an engineering approach that considers the entire interconnect path. As a key contributor to the Open Compute Project (OCP), Molex helps shape the open standards for next-generation hardware and provides a portfolio of solutions for the massive data loads, thermal challenges and density requirements of this new architecture.
On-chip I/O density and thermals
The move to CPO introduces critical challenges in managing heat and improving field serviceability. The Molex External Laser Source Interconnect System (ELSIS) is a complete, pluggable solution that moves the laser off the processor substrate. This approach uses a blind-mating design, which improves thermal performance, simplifies maintenance and enhances system safety by removing user access to optical fibres.
Internal Signal Integrity
Routing 224Gb-PAM-4 signals across a traditional PCB creates a major internal bottleneck due to signal degradation. BiPass technology?delivers a direct-to-I/O solution, routing high-speed signals through dedicated low-loss twinax cables that bypass the PCB. This preserves data integrity and can eliminate the need for costly, power-hungry retimers, reducing both system cost and thermal load.
Rack-level connectivity
Scaling the fabric across thousands of nodes demands a new generation of I/O ports for 1.6Tb+ speeds and extreme density. A portfolio of QSFP-DD and OSFP pluggable connectors deliver the essential industry-standard, high-density interfaces. These solutions offer robust, high-bandwidth connections while providing distinct advantages like the backward compatibility of QSFP-DD and the superior thermal management of the OSFP form factor.
Engineering the unified future
The shift toward a unified fabric represents a fundamental redesign of AI data centre connectivity, a necessary evolution to meet the demands of large-scale AI workloads. While software protocols continue to advance, the underlying physical requirements for moving terabits of data with minimal latency, power consumption and signal degradation remain persistent engineering challenges.
Ultimately, the performance of any unified fabric, regardless of its protocol, is dictated by the innovation, efficiency and reliability of its physical substructure.
Author biography:
Vivek Shah has been Sr. Director of Advanced Technologies at Molex since October 2009. Shah has held multiple engineering and management roles at Molex, including Director of New Product Development and Director of Engineering for Signal Integrity. Prior to joining Molex, Shah worked at Cisco as a Hardware Engineer, specializing in the design and analysis of high-speed interfaces. Shah holds a Master’s degree in Communications with a focus on Signal and Image Processing from Purdue University, as well as a Bachelor’s degree in Electrical and Electronics Engineering from Maharaja Sayajirao University.
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