Keysight Technologies has announced the launch of Chiplet PHY Designer 2025: its latest solution for high-speed digital chiplet design tailored for AI and data centre applications.
The software introduces simulation capabilities for the Universal Chiplet Interconnect Express (UCle) 2.0 standard and adds support for the Open Computer Project Bunch of Wires (BoW) standard. As an advanced, system-level chipset and die-to-die (D2D) design solution, Chiplet PHY Designer enables pre-silicon level validation.
Tracking the trend of the growth in complexity of both AI and data chips, ensuring reliable communication between chiplets is essential for performance. The industry is seeking to rectify this challenge through open, emerging standards like UCle and BoW that define the interconnects between chiplets within an advanced 2.5D/3D or laminate/advanced package.
Adopting these standards and verifying chiplets for compliance means designers are contributing to a growing system of chiplet interoperability, reducing costs and risks in semiconductor development.
Key benefits of the Chiplet PHY Designer 2025:
- Ensures interoperability: Verifies designs meet UCIe 2.0 and BoW standards, enabling seamless integration across advanced packaging ecosystems
- Accelerates time-to-market: Automates simulation and compliance testing setup, such as Voltage Transfer Function (VTF), simplifying chiplet design workflows
- Improves design accuracy: Provides insight into signal integrity, bit error rate (BER), and crosstalk analysis, reducing risks of costly silicon re-spins
- Optimises clocking designs: Supports advanced clocking scheme analysis, such as quarter-rate data rate (QDR), for precise synchronisation in high-speed interconnects
“Keysight EDA launched Chiplet PHY Designer one year ago as the industry’s first pre-silicon validation tool to provide in-depth modelling and simulation capabilities; this enabled chiplet designers to rapidly and accurately verify that their designs meet specifications before tapeout,” said Hee-Soo Lee, High-Speed Digital Segment Lead, Keysight EDA. “The latest release keeps pace with evolving standards like UCIe 2.0 and BoW while delivering new features, such as the QDR clocking scheme and systematic crosstalk analysis for single-ended buses.
“Engineers using Chiplet PHY Designer save time and avoid costly rework, ensuring their designs meet performance requirements before manufacturing. Early adopters, like Alphawave Semi, attest that Chiplet PHY Designer ensures seamless operation and interoperability for 2.5D/3D solutions available to their chiplet customers.”
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